• español
    • English
  • English 
    • español
    • English
  • Login
View Item 
  •   DSpace Home
  • Producción Científica
  • Artículos, capítulos, libros...UCO
  • View Item
  •   DSpace Home
  • Producción Científica
  • Artículos, capítulos, libros...UCO
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

Fast FPGA prototyping to explore and compare new SPWM strategies

Thumbnail
View/Open
11. Fast FPGA prototyping to explore and compare new SPWM strategies (2024).pdf (1.686Mb)
Author
Geninatti, Sergio R.
Ortiz-López, Manuel
Quiles-Latorre, Francisco Javier
Morales-Leal, Tomás
Gersnoviez, Andrés
Moreno-Muñoz, A.
Publisher
Elsevier
Date
2024
Subject
Terms—Spread Sprectrum
Supraharmonics
PWM
FPGA
METS:
Mostrar el registro METS
PREMIS:
Mostrar el registro PREMIS
Metadata
Show full item record
Abstract
This study presents a Flexible Test Bench (FTB) implemented with FPGA that synthesises of a large number of strategies that apply “Spread Spectrum” to reduce the energy of the fundamental harmonics present in a conventional Pulse Width Modulation (PWM). The FTB not only incorporates most of the known spread spectrum techniques but also allows to combine them and even to easily create new ones, thus providing a highly flexible test bench. The FTB has been described in standard VHDL, so it can be synthesised using any synthesis tool, and the number of logical resources used by each of them can be determined according to the spread spectrum strategy configured in its registers. Therefore, a tool is available to choose, according to the spectral response and the consumption of logic resources, the most suitable PWM spread spectrum strategy for each application. The particularity of the proposal is to have a unique hardware platform that allows the comparison of different techniques under the same physical implementation conditions since geometry and physical location are important when evaluating the conducted and radiated emission of the circuits. Another objective of our FTB is to solve in a unified way all the numerical aspects present in the FPGA-based implementation so that the numerical ranges and roundings used affect all the implemented techniques equally.
URI
http://hdl.handle.net/10396/27282
Fuente
IEEE Transactions on Circuits and Systems I: Regular Papers
Versión del Editor
http://dx.doi.org/10.1109/TCSI.2023.3347447
Collections
  • DACETE-Artículos, capítulos, libros...
  • Artículos, capítulos, libros...UCO

DSpace software copyright © 2002-2015  DuraSpace
Contact Us | Send Feedback
© Biblioteca Universidad de Córdoba
Biblioteca  UCODigital
 

 

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

LoginRegister

Statistics

View Usage Statistics

De Interés

Archivo Delegado/AutoarchivoAyudaPolíticas de Helvia

Compartir


DSpace software copyright © 2002-2015  DuraSpace
Contact Us | Send Feedback
© Biblioteca Universidad de Córdoba
Biblioteca  UCODigital